Transient-induced latchup in CMOS integrated circuits /

Transient-induced latchup in CMOS integrated circuits / Ming-Dou Ker and Sheng-Fu Hsu.

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"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the c...

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Bibliographic Details
Online Access: Full Text (via ProQuest)
Main Author: Ker, Ming-Dou
Other Authors: Hsu, Sheng-Fu
Format: Electronic eBook
Language:English
Published: [Piscataway, NJ] : Singapore ; Hoboken, NJ : IEEE Press ; John Wiley & Sons (Asia), ©2009.
Subjects:
Metal oxide semiconductors, Complementary > Defects.
Metal oxide semiconductors, Complementary > Reliability.
Metal oxide semiconductors, Complementary > Defects
Metal oxide semiconductors, Complementary > Reliability
Table of Contents:
  • 1. Introduction
  • 2. Physical Mechanism of TLU under the System-Level ESD Test
  • 3. Component-Level Measurement for TLU under System-Level ESD Considerations
  • 4. TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits
  • 5. TLU in CMOS ICs in the Electrical Fast Transient Test
  • 6. Methodology on Extracting Compact Layout Rules for Latchup Prevention
  • 7. Special Layout Issues for Latchup Prevention
  • 8. TLU Prevention in Power-Rail ESD Clamp Circuits
  • 9. Summary
  • Appendix A. Practical Application--Extractions of Latchup Design Rules in a 0.18-[mu]m 1.8 V/3.3V Silicided CMOS Process.

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