Leakage in nanometer CMOS technologies

Leakage in nanometer CMOS technologies [electronic resource] / [ed. by] Siva G. Narendra, Anantha Chandrakasan.

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Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...

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Bibliographic Details
Online Access: Full Text (via Springer)
Other Authors: Narendra, Siva G. (Siva Gurusami), 1971-, Chandrakasan, Anantha P.
Format: Electronic eBook
Language:English
Published: New York : Springer, 2006.
Series:Series on integrated circuits and systems.
Subjects:
Metal oxide semiconductors, Complementary > Design and construction.
Integrated circuits > Design and construction.
Electric leakage > Prevention.
Table of Contents:
  • Taxonomy of leakage : sources, impact, and solutions
  • Leakage dependence on input vector / Siva Narendra [and others]
  • Power gating and dynamic voltage scaling / Benton Calhoun, James Kao, and Anantha Chandrakasan
  • Methodologies for power gating / Kimiyoshi Usami and Takayasu Sakurai
  • Body biasing / Tadahiro Kuroda and Takayasu Sakurai
  • Process variation and adaptive design / Siva Narendra [and others]
  • Memory leakage reduction / Takayuki Kawahara and Kiyoo Itoh
  • Active leakage reduction and multi-performance devices / Siva Narendra [and others]
  • Impact of leakage power and variation on testing / Ali Keshavarzi and Kaushik Roy
  • Case study : leakage reduction in Hitachi/Renesas microprocessors / Masayuki Miyazaki, Hiroyuki Mizuno, and Takayuki Kawahara
  • Case study : leakage reduction in the Intel Xscale microprocessor / Lawrence Clark
  • Transistor design to reduce leakage / Sagar Suthram, Siva Narendra, and Scott Thompson.

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