Defect-oriented testing for nano-metric CMOS VLSI circuits

Defect-oriented testing for nano-metric CMOS VLSI circuits [electronic resource] / by Manoj Sachdev and José Pineda de Gyvez.

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"Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acc...

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Bibliographic Details
Online Access: Full Text (via Springer)
Main Author: Sachdev, Manoj
Other Authors: Pineda de Gyvez, José
Format: Electronic eBook
Language:English
Published: Dordrecht : Springer, ©2007.
Edition:2nd ed.
Series:Frontiers in electronic testing ; 34.
Subjects:
Metal oxide semiconductors, Complementary > Testing.
Metal oxide semiconductors, Complementary > Defects.
Integrated circuits > Very large scale integration > Testing.
Integrated circuits > Very large scale integration > Defects.

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Call Number: TK7871.99.M44 S23 2007eb
TK7871.99.M44 S23 2007eb Available

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