Formal Equivalence Checking and Design Debugging / by Shi-Yu Huang, Kwang-Ting (Tim) Cheng.
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to...
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| Online Access: |
Full Text (via Springer) |
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| Main Author: | |
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| Format: | eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
1998.
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| Series: | Frontiers in electronic testing ;
12. |
| Subjects: |
Internet
Full Text (via Springer)Online
| Call Number: |
TK7888.4
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| TK7888.4 | Available |