Hardness by design technique for field programmable gate arrays. [electronic resource]
FPGAs are an attractive alternative for many space-based computing operations. While radiation hardened FPGAs are available, SRAM-based FPGAs are susceptible to Single-Event Upsets (SEUs). Several FPGA design hardening techniques are investigated to improve the reliability of FPGA designs operating...
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| Online Access: |
Online Access |
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| Corporate Author: | |
| Format: | Government Document Electronic eBook |
| Language: | English |
| Published: |
Washington, D.C. : Oak Ridge, Tenn. :
United States. Department of Energy ; distributed by the Office of Scientific and Technical Information, U.S. Department of Energy,
2003.
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| Summary: | FPGAs are an attractive alternative for many space-based computing operations. While radiation hardened FPGAs are available, SRAM-based FPGAs are susceptible to Single-Event Upsets (SEUs). Several FPGA design hardening techniques are investigated to improve the reliability of FPGA designs operating in a radiation environment. The improved design reliability provided by these techniques are measured using a single-event upset simulation environment. |
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| Item Description: | Published through SciTech Connect. 01/01/2003. "la-ur-03-2848" Submitted to: 11th Annual NASA Symposium on VLSI Design, Coeur d'Alene, Idaho, May 28-29, 2003. Wirthlin, M. J.; Graham, P. S.; Caffrey, M. P.; Rollins, N. |
| Physical Description: | 6 p. : digital, PDF file. |