Digital system verification [electronic resource] : a combined formal methods and simulation framework / Lun Li, Mitchell A. Thornton.
Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates...
Saved in:
| Online Access: |
Full Text (via Morgan & Claypool) |
|---|---|
| Main Author: | |
| Other Authors: | |
| Other title: | Synthesis digital library of engineering and computer science. |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Morgan & Claypool Publishers,
©2010.
|
| Series: | Synthesis lectures on digital circuits and systems (Online) ;
# 27. |
| Subjects: |