Introduction to logic synthesis using Verilog HDL [electronic resource] / Robert B. Reese, Mitchell A. Thornton.
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and...
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| Online Access: |
Full Text (via Morgan & Claypool) |
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| Main Author: | |
| Other Authors: | |
| Other title: | Synthesis digital library of engineering and computer science. |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Morgan & Claypool Publishers,
©2006.
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| Edition: | 1st ed. |
| Series: | Synthesis lectures on digital circuits and systems (Online) ;
# 6. |
| Subjects: |
Internet
Full Text (via Morgan & Claypool)Online
| Call Number: |
TK7868.L6 R445 2006
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| TK7868.L6 R445 2006 | Available |