Systematic Design of Analog CMOS Circuits : Using Pre-Computed Lookup Tables / Paul G.A. Jespers, Boris Murmann.
Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables t...
Saved in:
| Online Access: |
Full Text (via Cambridge) |
|---|---|
| Main Authors: | , |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cambridge :
Cambridge University Press,
2017.
|
| Subjects: |
MARC
| LEADER | 00000cam a2200000Mi 4500 | ||
|---|---|---|---|
| 001 | in00000058412 | ||
| 006 | m o d | ||
| 007 | cr ||||||||||| | ||
| 008 | 160815s2017 enk o 001 0 eng d | ||
| 005 | 20230831181054.0 | ||
| 035 | |a (OCoLC)ceba1006810291 | ||
| 037 | |a ceba9781108125840 | ||
| 040 | |a OTZ |b eng |e rda |c OTZ |d MERER |d UIU |d MYG |d OCLCF |d U3W |d OCLCQ |d LVT |d K6U |d OCLCO |d SFB |d OCLCO |d OCLCQ | ||
| 019 | |a 1118507664 |a 1167298380 | ||
| 020 | |a 9781108125840 |q (ebook) | ||
| 020 | |a 1108125840 |q (ebook) | ||
| 020 | |z 9781107192256 |q (hardback) | ||
| 020 | |a 1107192250 | ||
| 020 | |a 9781107192256 | ||
| 035 | |a (OCoLC)1006810291 |z (OCoLC)1118507664 |z (OCoLC)1167298380 | ||
| 050 | 4 | |a TK7871.99.M44 |b J47 2017 | |
| 049 | |a GWRE | ||
| 100 | 1 | |a Jespers, Paul G. A., |e author. | |
| 245 | 1 | 0 | |a Systematic Design of Analog CMOS Circuits : |b Using Pre-Computed Lookup Tables / |c Paul G.A. Jespers, Boris Murmann. |
| 264 | 1 | |a Cambridge : |b Cambridge University Press, |c 2017. | |
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 500 | |a Title from publisher's bibliographic system (viewed on 26 Sep 2017). | ||
| 520 | |a Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS. | ||
| 505 | 0 | |a Cover -- Half-title -- Reviews -- Title page -- Copyright information -- Dedication -- Table of contents -- Symbols and Acronyms -- 1 Introduction -- 1.1 Motivation -- 1.2 The Analog Circuit Sizing Problem and the Proposed Approach -- 1.2.1 Square-Law Perspective -- 1.2.2 Capturing the Tradeoffs Using Lookup Tables -- 1.2.3 Generalization -- 1.2.4 VGS-agnostic design -- 1.2.5 Design in Weak Inversion -- 1.3 Content Overview -- 1.4 Prerequisites -- 1.5 Notation -- 1.6 References -- 2 Basic Transistor Modeling -- 2.1 The Charge Sheet Model (CSM) -- 2.1.1 The CSM Drain Current Equation -- 2.1.2 The Dependence of the Drain Current on the Drain Voltage -- 2.1.3 The Transconductance Efficiency gm/ID -- 2.2 The Basic EKV Model -- 2.2.1 The Basic EKV Equations -- 2.2.2 The Basic EKV Model for a Grounded-Source MOS Transistor -- 2.2.3 Strong and Weak Inversion Approximations of the EKV Model -- 2.2.4 Basic EKV Model Expressions for gm and gm/ID -- 2.2.5 EKV Parameter Extraction -- 2.3 Real Transistors -- 2.3.1 Real Drain Current Characteristics ID(VGS) and gm/ID -- 2.3.2 The Drain Saturation Voltage VDsat of Real Transistors -- 2.3.3 Impact of Bias Conditions on EKV Parameters -- 2.3.4 The Drain Current Characteristic ID(VDS) -- 2.3.5 The Output Conductance gds -- 2.3.6 The gds/ID Ratio -- 2.3.7 The Intrinsic Gain -- 2.3.8 MOSFET Capacitances and the Transit Frequency fT -- 2.4 Summary -- 2.5 References -- 3 Basic Sizing Using the gm/ID Methodology -- 3.1 Sizing an Intrinsic Gain Stage (IGS) -- 3.1.1 Circuit Analysis -- 3.1.2 Sizing Considerations -- 3.1.3 Sizing for Given L and gm/ID -- 3.1.4 Basic Tradeoff Exploration -- 3.1.5 Sizing in Weak Inversion -- 3.1.6 Sizing Using the Drain Current Density -- 3.1.7 Inclusion of Extrinsic Capacitances -- 3.2 Practical Common-Source Stages -- 3.2.1 Active Load -- 3.2.2 Resistive Load. | |
| 505 | 8 | |a 3.3 Differential Amplifier Stages -- 3.4 Summary -- 3.5 References -- 4 Noise, Distortion and Mismatch -- 4.1 Electronic Noise -- 4.1.1 Thermal Noise Modeling -- 4.1.2 Tradeoff between Thermal Noise, GBW and Supply Current -- 4.1.3 Thermal Noise from Active Loads -- 4.1.4 Flicker Noise (1/f Noise) -- 4.2 Nonlinear Distortion -- 4.2.1 Nonlinearity of the MOS Transconductance -- 4.2.2 Nonlinearity of the MOS Differential Pair -- 4.2.3 Inclusion of the Output Conductance -- 4.3 Random Mismatch -- 4.3.1 Modeling of Random Mismatch -- 4.3.2 Effect of Mismatch in a Current Mirror -- 4.3.3 Effect of Mismatch in a Differential Amplifier -- 4.4 Summary -- 4.5 References -- 5 Practical Circuit Examples I -- 5.1 Constant Transconductance Bias Circuit -- 5.2 High-Swing Cascoded Current Mirror -- 5.2.1 Sizing the Current Mirror Devices -- 5.2.2 Sizing the Cascode Bias Circuit -- 5.3 Low-Dropout Voltage Regulator -- 5.3.1 Low-Frequency Analysis -- 5.3.2 High-Frequency Analysis -- 5.4 RF Low-Noise Amplifier -- 5.4.1 Sizing for Low-Noise Figure -- 5.4.2 Sizing for Low-Noise Figure and Low Distortion -- 5.5 Charge Amplifier -- 5.5.1 Circuit Analysis -- 5.5.2 Optimization Assuming Constant Transit Frequency -- 5.5.3 Optimization Assuming Constant Drain Current -- 5.5.4 Optimization Assuming Constant Noise and Bandwidth -- 5.6 Designing for Process Corners -- 5.6.1 Biasing Considerations -- 5.6.2 Technology Evaluation over Process and Temperature -- 5.6.3 Possible Design Flows -- 5.7 Summary -- 5.8 References -- 6 Practical Circuit Examples II -- 6.1 Basic OTA for Switched-Capacitor Circuits -- 6.1.1 Small-Signal Circuit Analysis -- 6.1.2 Optimization Assuming Constant Noise and Bandwidth -- 6.1.3 Optimization in Presence of Slewing -- 6.2 Folded-Cascode OTA for Switched-Capacitor Circuits -- 6.2.1 Design Equations -- 6.2.2 Optimization Procedure. | |
| 505 | 8 | |a 6.2.3 Optimization in Presence of Slewing -- 6.3 Two-Stage OTA for Switched-Capacitor Circuits -- 6.3.1 Design Equations -- 6.3.2 Optimization Procedure -- 6.3.3 Optimization in Presence of Slewing -- 6.4 Simplified Design Flows -- 6.4.1 Folded-Cascode OTA -- 6.4.2 Two-Stage OTA -- 6.5 Sizing Switches -- 6.6 Summary -- 6.7 References -- Appendix 1: The EKV Parameter Extraction Algorithm -- A.1.1 Review of Equations -- A.1.2 Parameter Extraction Algorithm -- A.1.3 Matlab Function XTRACT.m -- A.1.4 Parameter Extraction Example -- A.1.5 Matlab Function XTRACT2.m -- A.1.6 Corner Parameter Extraction -- A.1.7 Conclusion -- A.1.8 References -- Appendix 2: Lookup Table Generation and Usage -- A.2.1 Lookup Table Generation -- A.2.1.1 Configuration File -- A.2.1.2 Generating Lookup Tables for a New Technology -- A.2.2 Matlab Function lookup.m -- A.2.3 Matlab Function lookupVGS.m -- A.2.4 Lookup of Ratios with Non-monotonic Vectors -- A.2.5 LookupVGS with Non-monotonic gm/ID Vector -- A.2.6 Passing Design Variables to the Simulator -- A.2.7 References -- Appendix 3: Layout Dependence -- A.3.1 Introduction to Layout Dependent Effects (LDE) -- A.3.2 Transistor Finger Partitioning -- A.3.3 Width Dependence of Parameter Ratios -- Index. | |
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Computer-aided design. | |
| 650 | 0 | |a Integrated circuits |x Computer-aided design. | |
| 650 | 7 | |a Integrated circuits |x Computer-aided design. |2 fast |0 (OCoLC)fst00975538 | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary |x Computer-aided design. |2 fast |0 (OCoLC)fst01017637 | |
| 700 | 1 | |a Murmann, Boris, |e author. | |
| 776 | 0 | 8 | |i Print version: |z 9781107192256 |
| 856 | 4 | 0 | |u https://colorado.idm.oclc.org/login?url=https://doi.org/10.1017/9781108125840 |z Full Text (via Cambridge) |
| 915 | |a M | ||
| 956 | |a Cambridge EBA | ||
| 956 | |b Cambridge EBA ebooks Complete Collection | ||
| 998 | |b New collection CUP.ebaebookscomplete | ||
| 994 | |a 92 |b COD | ||
| 999 | f | f | |s 717673aa-e55a-44e7-8fbb-da3dcd9ec8b6 |i 1f524362-97af-4feb-9663-afc2dd07a1ca |
| 952 | f | f | |p Can circulate |a University of Colorado Boulder |b Online |c Online |d Online |h Library of Congress classification |i web |