Writing testbenches : functional verification of HDL models /

Writing testbenches : functional verification of HDL models / by Janick Bergeron.

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Mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven...

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Bibliographic Details
Online Access: Full Text (via Springer)
Main Author: Bergeron, Janick (Author)
Format: eBook
Language:English
Published: New York : Springer Science+Business Media, LLC, 2003.
Edition:Second Edition.
Subjects:
Computer hardware description languages.
Integrated circuits > Verification.
Table of Contents:
  • 1 What is Verification?
  • What is a Testbench?
  • The Importance of Verification
  • Reconvergence Model
  • The Human Factor
  • What Is Being Verified?
  • Functional Verification Approaches
  • Testing Versus Verification
  • Design and Verification Reuse
  • The Cost of Verification
  • Summary
  • 2 Verification Tools
  • Linting Tools
  • Simulators
  • Verification Intellectual Property
  • Waveform Viewers
  • Functional Coverage
  • Verification Languages
  • Assertions
  • Revision Control
  • Issue Tracking
  • Metrics
  • Summary
  • 3 The Verification Plan
  • The Role of the Verification Plan
  • Levels of Verification
  • Verification Strategies
  • From Specification to Features
  • Directed Testbenches Approach
  • Coverage-Driven Random-Based Approach
  • Summary
  • 4 High-Level Modeling
  • Behavioral versus RTL Thinking
  • You Gotta Have Style!
  • Structure of Behavioral Code
  • Data Abstraction
  • Object-Oriented Programming
  • Aspect-Oriented Programming
  • The Parallel Simulation Engine
  • Race Conditions
  • Verilog Portability Issues
  • Summary
  • 5 Stimulus and Response
  • Reference Signals
  • Simple Stimulus
  • Simple Output
  • Complex Stimulus
  • Bus-Functional Models
  • Response Monitors
  • Transaction-Level Interface
  • Summary
  • 6 Architecting Testbenches
  • Test Harness
  • VHDL Test Harness
  • Design Configuration
  • Self-Checking Testbenches
  • Directed Stimulus
  • Random Stimulus
  • Summary
  • 7 Simulation Management
  • Behavioral Models
  • Pass or Fail?
  • Managing Simulations
  • Regression
  • Summary
  • Appendix A Coding Guidelines
  • Directory Structure
  • VHDL Specific
  • Verilog Specific
  • General Coding Guidelines
  • Comments
  • Layout
  • Syntax
  • Debugging
  • Naming Guidelines
  • Capitalization
  • Identifiers
  • Constants
  • HDL & HVL Specific
  • Filenames
  • HDL Coding Guidelines
  • Structure
  • Layout
  • VHDL Specific
  • Verilog Specific
  • Appendix B Glossary
  • Afterwords.

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