Writing testbenches : functional verification of HDL models / by Janick Bergeron.
Mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven...
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Full Text (via Springer) |
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| Format: | eBook |
| Language: | English |
| Published: |
New York :
Springer Science+Business Media, LLC,
2003.
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| Edition: | Second Edition. |
| Subjects: |
MARC
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| 100 | 1 | |a Bergeron, Janick, |e author. | |
| 245 | 1 | 0 | |a Writing testbenches : |b functional verification of HDL models / |c by Janick Bergeron. |
| 250 | |a Second Edition. | ||
| 264 | 1 | |a New York : |b Springer Science+Business Media, LLC, |c 2003. | |
| 264 | 4 | |c ©2003. | |
| 300 | |a 1 online resource (XXX, 478 p.) | ||
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| 505 | 0 | |a 1 What is Verification? -- What is a Testbench? -- The Importance of Verification -- Reconvergence Model -- The Human Factor -- What Is Being Verified? -- Functional Verification Approaches -- Testing Versus Verification -- Design and Verification Reuse -- The Cost of Verification -- Summary -- 2 Verification Tools -- Linting Tools -- Simulators -- Verification Intellectual Property -- Waveform Viewers -- Functional Coverage -- Verification Languages -- Assertions -- Revision Control -- Issue Tracking -- Metrics -- Summary -- 3 The Verification Plan -- The Role of the Verification Plan -- Levels of Verification -- Verification Strategies -- From Specification to Features -- Directed Testbenches Approach -- Coverage-Driven Random-Based Approach -- Summary -- 4 High-Level Modeling -- Behavioral versus RTL Thinking -- You Gotta Have Style! -- Structure of Behavioral Code -- Data Abstraction -- Object-Oriented Programming -- Aspect-Oriented Programming -- The Parallel Simulation Engine -- Race Conditions -- Verilog Portability Issues -- Summary -- 5 Stimulus and Response -- Reference Signals -- Simple Stimulus -- Simple Output -- Complex Stimulus -- Bus-Functional Models -- Response Monitors -- Transaction-Level Interface -- Summary -- 6 Architecting Testbenches -- Test Harness -- VHDL Test Harness -- Design Configuration -- Self-Checking Testbenches -- Directed Stimulus -- Random Stimulus -- Summary -- 7 Simulation Management -- Behavioral Models -- Pass or Fail? -- Managing Simulations -- Regression -- Summary -- Appendix A Coding Guidelines -- Directory Structure -- VHDL Specific -- Verilog Specific -- General Coding Guidelines -- Comments -- Layout -- Syntax -- Debugging -- Naming Guidelines -- Capitalization -- Identifiers -- Constants -- HDL & HVL Specific -- Filenames -- HDL Coding Guidelines -- Structure -- Layout -- VHDL Specific -- Verilog Specific -- Appendix B Glossary -- Afterwords. | |
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a Mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. | ||
| 546 | |a English. | ||
| 588 | |a Description based on print version record. | ||
| 650 | 0 | |a Computer hardware description languages. | |
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| 650 | 7 | |a Integrated circuits |x Verification. |2 fast |0 (OCoLC)fst00975600. | |
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