Writing testbenches : functional verification of HDL models / by Janick Bergeron.
Mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven...
Saved in:
| Online Access: |
Full Text (via Springer) |
|---|---|
| Main Author: | |
| Format: | eBook |
| Language: | English |
| Published: |
New York :
Springer Science+Business Media, LLC,
2003.
|
| Edition: | Second Edition. |
| Subjects: |
| Summary: | Mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. |
|---|---|
| Item Description: | Bibliographic Level Mode of Issuance: Monograph. |
| Physical Description: | 1 online resource (XXX, 478 p.) |
| Bibliography: | Includes bibliographical references and index. |
| ISBN: | 1461503027 9781461503026 |