Progress in VLSI design and test [electronic resource] : 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings / Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay (eds.)
This book constitutes the refereed proceedings of the 16th International Symposium on VSLI Design and Test, VDAT 2012, held in Shibpur, India, in July 2012. The 30 revised regular papers presented together with 10 short papers and 13 poster sessions were carefully selected from 135 submissions. The...
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| Other title: | VDAT 2012. |
| Format: | Electronic Conference Proceeding eBook |
| Language: | English |
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Berlin ; New York :
Springer,
©2012.
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| Series: | Lecture notes in computer science ;
7373. LNCS sublibrary. Theoretical computer science and general issues. |
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Table of Contents:
- An Efficient High Frequency and Low Power Analog Multiplier in Current Domain / Anu Gupta and Subhrojyoti Sarkar
- Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator / Biswajit Maity and Pradip Mandal
- Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm / Priyanka Choudhury and Sambhu Nath Pradhan
- Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding / Rahul Shrestha and Roy Paily
- Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects / Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu and Manoj Kumar Majumder
- Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET / Ashutosh Nandi, Ashok K. Saxena and Sudeb Dasgupta
- Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips / R. Jayagowri and K.S. Gurumurthy
- Post-bond Stack Testing for 3D Stacked IC / Surajit Kumar Roy, Dona Roy, Chandan Giri and Hafizur Rahaman
- Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker / Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar and Chittaranjan R. Mandal
- Design of High Speed Vedic Multiplier for Decimal Number System / Prabir Saha, Arindam Banerjee, Anup Dandapat and Partha Bhattacharyya
- An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol / Mamata Dalui and Biplab K. Sikdar
- An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs / Debapriya Basu Roy and Debdeep Mukhopadhyay
- Arithmetic Algorithms for Ternary Number System / Subrata Das, Partha Sarathi Dasgupta and Samar Sensarma
- SOI MEMS Based Over-Sampling Accelerometer Design with & Delta; & Epsilon;Output / Dushyant Juneja, Sougata Kar, Procheta Chatterjee and Siddhartha Sen
- Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting / Goutam Rana, Samir Kumar Lahiri and Chirasree Roy Chaudhuri
- Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin / Chandrabhan Kushwah and Santosh K. Vishvakarma
- Workload Driven Power Domain Partitioning / Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and Chittaranjan R. Mandal
- Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit / Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee and Chandan Kumar Sarkar.
- A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL / Manas Kumar Hati and Tarun Kanti Bhattacharyya
- ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits / Jaynarayan T. Tudu, Deepak Malani and Virendra Singh
- Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter / Manodipan Sahoo and Bharadwaj Amrutur
- Effect of Malicious Hardware Logic on Circuit Reliability / Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay and Pranav Singh
- A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power / P.R. Sruthi and M. Nirmala Devi
- Reusable and Scalable Verification Environment for Memory Controllers / Kiran Kumar Abburi, Siva Subrahmanya Evani, Sajeev Thomas and Anup Aprem
- Design of a Fault-Tolerant Conditional Sum Adder / Atin Mukherjee and Anindya Sundar Dhar
- SEU Tolerant Robust Latch Design / Mohammed Shayan, Virendra Singh, Adit D. Singh and Masahiro Fujita
- Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors / Debaprasad Das, Avisek Sinha Roy and Hafizur Rahaman
- High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves / Ayantika Chatterjee and Indranil Sengupta
- A 4 x 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology / Mahendra Sakare, Mohit Singh and Shalabh Gupta
- VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m)Using Dual Bases / Hafizur Rahaman, Jimson Mathew, A.M. Jabir and Dhiraj K. Pradhan
- A Synthesis Method for Quaternary Quantum Logic Circuits / Sudhindu Bikash Mandal, Amlan Chakrabarti and Susmita Sur-Kolay
- On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits / Lafifa Jamal, Md. Masbaul Alam Polash, M.A. Mottalib and Hafiz Md. Hasan Babu
- Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects / Debaprasad Das and Hafizur Rahaman
- A Fast FPGA Based Architecture for Sobel Edge Detection / Santanu Halder, Debotosh Bhattacharjee, Mita Nasipuri and Dipak Kumar Basu
- Speech Processor Design for Cochlear Implants / Arun Kumarappan and P.V. Ramakrishna
- An Efficient Technique for Longest Prefix Matching in Network Routers / Rekha Govindaraj, Indranil Sengupta and Santanu Chattopadhyay.
- A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts / Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan and Chittaranjan R. Mandal
- Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations / Sanga Chaki and Chandan Giri
- Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip / Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta and Santanu Chattopadhyay
- An Efficient Multiplexer in Quantum-dot Cellular Automata / Bibhash Sen, Manojit Dutta, Divyam Saran and Biplab K. Sikdar
- Integrated Placement and Optimization Flow for Structured and Regular Logic / Vikram Singh Saun, Suman Chatterjee and Anand Arunachalam
- A Novel Symbol Estimation Algorithm for LTE Standard / K Kalyani and S. Rajaram
- Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance / Naushad Alam, Bulusu Anand and Sudeb Dasgupta
- A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes / Biswajit Patra, Santan Chattopadhyay and Amlan Chakrabarti
- Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic / P. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram and P. Kalpana
- Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic / Sauvagya Ranjan Sahoo and Kamala Kanta Mahapatra
- Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks / Arpan Mondal, Santosh Ghosh, Abhijit Das and Dipanwita Roy Chowdhury
- Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET / Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur and Manoj Kumar Majumder
- VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark / Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee and Hafizur Rahaman, et al.
- A Photonic Network on Chip with CDMA Links / Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui and Hafizur Rahaman
- Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor / Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman and Partha Sarathi Dasgupta
- Routing in NoC on Diametrical 2D Mesh Architecture / Prasun Ghosal and Tuhin Subhra Das
- Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology (Invited Paper) / Rolf Drechsler and Robert Wille
- Power Problems in VLSI Circuit Testing / Farhana Rashid and Vishwani D. Agrawal.
- An Efficient High Frequency and Low Power Analog Multiplier in Current Domain / Anu Gupta and Subhrojyoti Sarkar
- Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator / Biswajit Maity and Pradip Mandal
- Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm / Priyanka Choudhury and Sambhu Nath Pradhan
- Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding / Rahul Shrestha and Roy Paily
- Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects / Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu and Manoj Kumar Majumder
- Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET / Ashutosh Nandi, Ashok K. Saxena and Sudeb Dasgupta
- Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips / R. Jayagowri and K.S. Gurumurthy
- Post-bond Stack Testing for 3D Stacked IC / Surajit Kumar Roy, Dona Roy, Chandan Giri and Hafizur Rahaman
- Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker / Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar and Chittaranjan R. Mandal
- Design of High Speed Vedic Multiplier for Decimal Number System / Prabir Saha, Arindam Banerjee, Anup Dandapat and Partha Bhattacharyya
- An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol / Mamata Dalui and Biplab K. Sikdar
- An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs / Debapriya Basu Roy and Debdeep Mukhopadhyay
- Arithmetic Algorithms for Ternary Number System / Subrata Das, Partha Sarathi Dasgupta and Samar Sensarma
- SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output / Dushyant Juneja, Sougata Kar, Procheta Chatterjee and Siddhartha Sen
- Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting / Goutam Rana, Samir Kumar Lahiri and Chirasree Roy Chaudhuri
- Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin / Chandrabhan Kushwah and Santosh K. Vishvakarma
- Workload Driven Power Domain Partitioning / Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta and Chittaranjan R. Mandal
- Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit / Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee and Chandan Kumar Sarkar.