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|a TK5105.546
|b .L69 2011
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|a Low power networks-on-chip
|h [electronic resource] /
|c Cristina Silvano, Marcello Lajolo, Gianluca Palermo, editors.
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260 |
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|a New York :
|b Springer Science+Business Media, LLC,
|c ©2011.
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|a 1 online resource (xix, 287 pages) :
|b illustrations (some color)
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|a Includes bibliographical references and index.
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|a pt. 1. Low-level design techniques -- pt. 2. System-level design techniques -- pt. 3. Future and emerging technologies.
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|a Print version record.
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|a Networks on a chip.
|0 http://id.loc.gov/authorities/subjects/sh2008004518.
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|a Networks on a chip.
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|a Lajolo, Marcello.
|0 http://id.loc.gov/authorities/names/no2011096740
|1 http://isni.org/isni/0000000120749770.
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|a Palermo, Gianluca.
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|i Print version:
|t Low power networks-on-chip.
|d New York : Springer, 2011
|w (DLC) 2010935810.
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|e TK5105.546 .L69 2011
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|n 1
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