Hardware/software codesign [electronic resource] / by Patrick R. Schaumont.
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Full Text (via Springer) |
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
New York ; London :
Springer,
2010.
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| Subjects: |
Table of Contents:
- A Practical Introduction to Hardware/Software Codesign; Preface; Contents; Part I Basic Concepts; 1 The Nature of Hardware and Software; 1.1 Introducing Hardware/Software Codesign; 1.1.1 Hardware; 1.1.2 Software; 1.1.3 Hardware and Software; 1.1.4 Defining Hardware/Software Codesign; 1.2 The Quest for Energy Efficiency; 1.2.1 Relative Performance; 1.2.2 Energy Efficiency; 1.3 The Driving Factors in Hardware/Software Codesign; 1.4 The Hardware
- Software Codesign Space; 1.4.1 The Platform Design Space; 1.4.2 Application Mapping; 1.5 The Dualism of Hardware Design and Software Design.
- 1.6 More on Modeling1.6.1 Abstraction Levels; 1.7 Concurrency and Parallelism; 1.8 Summary; 1.9 Further Reading; 1.10 Problems; 2 Data Flow Modeling and Implementation; 2.1 The Need for Concurrent Models: An Example; 2.1.1 Tokens, Actors, and Queues; 2.1.2 Firing Rates, Firing Rules, and Schedules; 2.1.3 Synchronous Data Flow Graphs; 2.1.4 SDF Graphs are Determinate; 2.2 Analyzing Synchronous Data Flow Graphs; 2.2.1 Deriving Periodic Admissible Sequential Schedules; 2.2.2 Example: Euclid's Algorithm as an SDF Graph; 2.3 Control Flow Modeling and the Limitations of Data Flow Models.
- 2.3.1 Emulating Control Flow with SDF Semantics2.3.2 Extending SDF Semantics; 2.4 Software Implementation of Data Flow; 2.4.1 Converting Queues and Actors into Software; 2.4.1.1 FIFO Queues; 2.4.1.2 Actors; 2.4.2 Sequential Targets with Dynamic Schedule; 2.4.2.1 Single-Thread Dynamic Schedules; 2.4.2.2 MultiThread Dynamic Schedules; 2.4.3 Sequential Targets with Static Schedule; 2.5 Hardware Implementation of Data Flow; 2.5.1 Single-Rate SDF Graphs; 2.5.2 Pipelining; 2.5.3 Multirate Expansion; 2.6 Summary; 2.7 Further Reading; 2.8 Problems; 3 Analysis of Control Flow and Data Flow.
- 3.1 Data and Control Edges of a C Program3.2 Implementing Data and Control Edges; 3.3 Contruction of the Control Flow Graph; 3.4 Construction of the Data Flow Graph; 3.5 Application: Translating C to Hardware; 3.5.1 Designing the Datapath; 3.5.2 Designing the Controller; 3.6 Single-Assignment Programs; 3.7 Summary; 3.8 Further Reading; 3.9 Problems; Part II The Design Space of Custom Architectures; 4 Finite State Machine with Datapath; 4.1 Cycle-Based Bit-Parallel Hardware; 4.1.1 Wires and Registers; 4.1.2 Precision and Sign; 4.1.3 Hardware Mapping of Expressions; 4.2 Hardware Modules.
- 4.3 Finite State Machines4.4 Finite State Machines with Datapath; 4.4.1 Modeling; 4.4.2 An FSMD is Not Unique; 4.4.3 Implementation; 4.5 Simulation and RTL Synthesis of FSMD; 4.5.1 Simulation; 4.5.2 Code Generation and Synthesis; 4.6 Proper FSMD; 4.7 Language Mapping for FSMD by Example; 4.7.1 GCD in GEZEL; 4.7.2 GCD in Verilog; 4.7.3 GCD in VHDL; 4.7.4 GCD in SystemC; 4.8 Summary; 4.9 Further Reading; 4.10 Problems; 5 Microprogrammed Architectures; 5.1 Limitations of Finite State Machines; 5.1.1 State Explosion; 5.1.2 Exception Handling; 5.1.3 Runtime Flexibility; 5.2 Microprogrammed Control.